अंग्रेज़ी में BRANCH INSTRUCTION का क्या अर्थ होता है?
शाखा (कंप्यूटर विज्ञान)
एक शाखा कंप्यूटर प्रोग्राम में एक अनुदेश है, जो कंप्यूटर द्वारा निष्पादित होने पर, कंप्यूटर को एक अलग निर्देश अनुक्रम के निष्पादन को शुरू करने के लिए प्रेरित कर सकता है। शाखा एक शाखा अनुदेश निष्पादित करने के कारण भिन्न निर्देश अनुक्रम के प्रारंभिक निष्पादन का भी उल्लेख कर सकता है। एक शाखा अनुदेश या तो एक बिना शर्त शाखा हो सकती है, जो हमेशा शाखाओं में होता है, या एक सशर्त शाखा होती है, जो कि कुछ स्थितियों के आधार पर शाखाएं उत्पन्न नहीं हो सकती या हो सकती है। एक प्रोग्राम निष्पादित करते समय, एक कंप्यूटर अनुक्रम में निर्देशों को लाएगा और निष्पादित करेगा जब तक कि उसे शाखा अनुदेश का सामना न करे। यदि निर्देश एक बिना शर्त शाखा है, या यह सशर्त है और स्थिति संतुष्ट है, तो शाखा शाखा अनुदेश द्वारा निर्दिष्ट के रूप में कंप्यूटर शाखा जाएगा। हालांकि, अगर शाखा अनुदेश सशर्त है और स्थिति संतुष्ट नहीं है, कंप्यूटर शाखा नहीं करेगा; इसके बजाय, यह वर्तमान अनुदेश अनुक्रम निष्पादित करना जारी रखेगा, जो कि सशर्त शाखा अनुदेश के बाद अनुदेश के साथ शुरू होता है।
अंग्रेज़ीशब्दकोश में branch instruction की परिभाषा
शब्दकोश में शाखा अनुदेश की परिभाषा एक मशीन-भाषा या विधानसभा-भाषा निर्देश है, जो कंप्यूटर को किसी अन्य अनुदेश के लिए शाखा देता है।
अंग्रेज़ी किताबें जो «BRANCH INSTRUCTION» से संबंधित हैं
निम्नलिखित ग्रंथसूची चयनों में
branch instruction का उपयोग पता करें।
branch instruction aसे संबंधित किताबें और अंग्रेज़ी साहित्य में उसके उपयोग का संदर्भ प्रदान करने वाले उनके संक्षिप्त सार।.
1
PIC Microcontroller: An Introduction to Software and ...
When a branch instruction is being executed, the 8- bit signed value contained in
the branch instruction is added to the current PC. When the signed value is
negative, the branch is backward. Otherwise, the branch is forward. The branch ...
2
Dictionary of Computer Science, Engineering and Technology
Typical examples from common languages include the if-then-else, case, switch,
and guarded condition. branch instruction an instruction used to modify the
instruction execution sequence of the CPU. The transfer of control to another ...
3
Speculative Execution in High Performance Computer Architectures
processor - the first Reduced Instruction Set Computer (RISC) - has a Delayed
Branch instruction [22, 12]. 3.3.1 The Delayed Branch Instruction The delayed
branch instruction causes instruction flow to be diverted after the instruction that ...
David Kaeli, Pen-Chung Yew,
2005
4
Fortress Rochester: The Inside Story of the IBM ISeries
If there is a match, the instruction fetch stage knows it has fetched a branch
instruction, although the actual instruction decode will not occur until the next
stage. The instruction fetch stage then uses the branch target address stored in
the table ...
5
Inside the Machine: An Illustrated Introduction to ...
Branch Instructions and the Fetch-Execute Loop Now that we have looked at the
basics of branching, we can modify our three- step summary of program
execution to include the possibility of a branch instruction: 1. Fetch the next
instruction ...
6
Comprehensive Dictionary of Electrical Engineering
Used to predict the outcome of branch instructions when these instructions are
next encountered. Also more accurately called a branch target buffer. branch
instruction an instruction is used to modify the instruction execution sequence of
the ...
Phillip A. Laplante,
1999
7
Digital Design: A Systems Approach
With the instruction sequencer, inputs are tested by the branch logic as directed
by a branch instruction from the current microinstruction. As a result of this test,
the sequencer either branches (by selecting the branch target field as the next ...
William J. Dally, R. Curtis Harting,
2012
8
Computer Architecture: A Quantitative Approach
This technique was heavily used in early RISC processors and works reasonably
well in the five-stage pipeline. In a delayed branch, the execution cycle with a
branch delay of one is branch instruction sequential successor1 branch target if ...
John L. Hennessy, David A. Patterson,
2006
9
Readings in Computer Architecture
IS A BRANCH INSTRUCTION CURRENTLY BEING DECODED? IS THIS A
CONDITIONAL BRANCH INSTRUCTION? 1. GENERATE AND SET ASIDE THE
ADDRESS OF THE TARGET OF THE CONDITIONAL BRANCH 2. DO THE "
BACK ...
Mark Donald Hill, Norman Paul Jouppi, Gurindar Sohi,
2000
10
Embedded Computer Systems: Architectures, Modeling, and ...
identifying branch instruction. If there is a scheme for identifying branch
instructions, it isn't needed to access the branch logic every cycle. Accordingly,
the energy to access the branch logic can be reduced dramatically. L.D F0,0(R1)
ADD.D F6 ...
«BRANCH INSTRUCTION» पद को शामिल करने वाली समाचार सामग्रियां
इसका पता लगाएं कि राष्ट्रीय और अंतर्राष्ट्रीय प्रेस ने निम्नलिखित समाचार सामग्रियों के बारे में क्या चर्चा की है और इस संदर्भ में
branch instruction पद का कैसे उपयोग किया है।
The pros and cons of dynamic translation architectures
If the hot address is a branch instruction, the translator may attempt to unroll the loop to both avoid the need to use branch prediction and ... «New Electronics, मई 15»
Opening statements, witnesses take stand in trial for man accused of …
A video was shown in court of the officer giving Branch instruction's and demonstrating what to do for the field sobriety test. Branch begins to do ... «WAFB.com, अक्टूबर 14»
ARM's Cortex M: Even Smaller and Lower Power CPU Cores
In the event the decoder encounters a branch instruction, there's a speculative instruction fetch that grabs the instruction at the branch target. «AnandTech, अगस्त 14»
Obama's next steps on immigration
In the realm of fixing inequities in the immigration system, President Obama's use of the executive branch instruction has been the most ... «The Week Magazine, अप्रैल 14»
The mobile security model is broken: V-Key
"[I] changed the branch instruction to essentially bypass the check, and I patched it, literally modifying one byte in the application." Gan did ... «ZDNet, जून 13»
Extreme Code Density: Energy Savings and Methods
... a comparison between two variables) that sets some flag, and a second conditional branch instruction that uses that flag (e.g., branch if a greater flag is set). «Chip Design Magazine, फरवरी 13»
Setting traps with SLIP, king of the mainframe debugging tools
SLIP recognizes a Successful Branch (SBT) condition when the CPU executes a successful branch instruction within the range of addresses. This trap would be ... «TechTarget, जुलाई 12»
What goes on inside the CPU
Pipelining can also fail when a conditional branch instruction is encountered – that is, where the flow of the program is potentially diverted ... «PC Authority, फरवरी 12»
Basic disassembly: Decoding the opcode
With this assumption, we can consult the extended mnemonic section (page 43 in the summary) and infer the original branch instruction may have been coded ... «SearchDataCenter.com, सितंबर 11»
Oracle's Sparc T4 chip: Will you pay Larry's premium?
... for Oracle software, including user-level cryptographic instructions, a pause instruction, and a fused compare-branch instruction. «Register, अगस्त 11»